descripción del trabajo

We are working with a leading supplier of RISC-V IP cores, looking to expand their RTL team. This position would be full time onsite in Barcelona. We are seeking individuals with either a solid RTL background or expertise in architecture/microarchitecture. We're particularly interested in those who want to work on various aspects of RISC-V design for advanced technology nodes. Key focus areas include the processor pipeline, data cache, instruction cache, L2 pipeline, and a custom memory controller. We value engineers who have a deep understanding of the problems at hand and can translate those insights into RTL solutions.

Key Requirements:

• Bachelor's degree in Computer Science
• English C1
• Knowledge in Verilog
• Scripting
• 5+ years experience as an RTL Engineer

Keywords:

RTL Engineer / RISC-V / RTL Coding / RTL Development / Verilog

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